1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to latch circuits.
2. Description of the Related Art
Latch circuits are commonly known in the electronic arts. Typical latch circuits have two stable states and may thus be usable for storing a bit of logical information (e.g., a logic 0 or a logic 1). Latch circuits come in a wide variety of forms, from very simple latches to more complex circuits. Latches may also be dynamic (e.g., having a precharge phase and an evaluation phase during operations) and static (e.g., having no precharge).
One type of latch circuit is known as a set-dominant (or zero-keeper) latch. In various embodiments, a set-dominant latch is a dynamic latch that captures a dynamic input that operates in a precharge phase and an evaluation phase and supplies a static output corresponding to the dynamic input. The precharge phase occurs during a first phase of a clock signal (e.g., when the clock is low), while the evaluation phase is performed during a second phase of the clock signal (e.g., when the clock is high). A set-dominant latch can be used in conjunction with domino dynamic circuits. Furthermore, when used in conjunction with domino logic, a set-dominant latch provides a path to convey logic signals from dynamic logic to static logic.
The set-dominant latch is susceptible to a glitch on the output that can occur when the clock to the latch transitions to the evaluate phase and the dynamic input signal has not yet been precharged. The glitch can cause unnecessary power consumption, reducing battery life in mobile devices.